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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
5.5.3
Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 5-4. Timing Requirements for CLKIN (1)
(2)
(see Figure 5-9 )
NO.
CV DD = 1.05 V
MIN NOM
MAX
MIN
CV DD = 1.3 V
NOM
MAX
UNIT
88.577,
88.577,
1
t c(CLKIN)
Cycle time, external clock driven on
CLKIN
83.333,
or
83.333,
or
ns
81.380
81.380
2
3
t w(CLKINH) Pulse width, CLKIN high
t w(CLKINL) Pulse width, CLKIN low
0.466 *
t c(CLKIN)
0.466 *
t c(CLKIN)
0.466 *
t c(CLKIN)
0.466 *
t c(CLKIN)
ns
ns
4
t t(CLKIN)
Transition time, CLKIN
4
4
ns
(1)
(2)
The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for
CPU operating frequency.
The reference points for the rise and fall transitions are measured at V IL MAX and V IH MIN.
1
4
1
2
CLKIN
3
4
Figure 5-9. CLKIN Timing
Table 5-5. Switching Characteristics Over Recommended Operating Conditions for CLKOUT (1)
(see Figure 5-10 )
(2)
CV DD = 1.05 V
CV DD = 1.3 V
NO.
PARAMETER
V DDA_PLL = 1.3 V
MIN
MAX
V DDA_PLL = 1.3 V
MIN
MAX
UNIT
1
t c(CLKOUT)
Cycle time, CLKOUT
P
16.67 or
13.33
P
10 or 8.3
ns
2
3
4
5
t w(CLKOUTH)
t w(CLKOUTL)
t t(CLKOUTR)
t t(CLKOUTF)
Pulse duration, CLKOUT high
Pulse duration, CLKOUT low
Transition time (rise), CLKOUT
Transition time (fall), CLKOUT
0.466 *
t c(CLKOUT)
0.466 *
t c(CLKOUT)
5
5
0.466 *
t c(CLKOUT)
0.466 *
t c(CLKOUT)
5
5
ns
ns
ns
ns
(1)
(2)
The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN.
P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.
2
1
5
CLKOUT
3
4
Figure 5-10. CLKOUT Timing
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Peripheral Information and Electrical Specifications
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